// operation: 0 = fill with zeroes
//            1 = sign extend
module extender_16to32(in16, out32, operation);
  parameter INSIZE = 16, OUTSIZE = 32;
  
  input [INSIZE-1:0] in16;
  input operation;
  output [OUTSIZE-1:0] out32;
  reg [OUTSIZE-1:0] out32;
  
  // set the 15:0 of out32 to the digits of in16
  always@(in16 or out32 or operation)
  begin
    case(operation)
	1'b0: assign out32 = {{ OUTSIZE-INSIZE {0}}, in16};   // fill with zeroes
	1'b1: assign out32 = {{ OUTSIZE-INSIZE {in16[INSIZE-1]}}, in16}; // sign extend
	endcase
  end 
  
endmodule

// test bench
/*module extender_testbench();
    reg[15:0]   in;
	reg op;
    wire[31:0]	out;    

    extender_16to32 ex(in,out,op);

    initial begin
        $monitor ($time,"\top=%b\tin=%b\tout=%b",op,in,out);
        in = 16'd150; op = 1'b0;
		#10 in = -16'd150; 
		#10 op = 1'b1; 
		#10 in = 16'd150; op = 1'b0;
		#10 in = 16'd32767; op = 1'b1;  // max value for 16-bit signed integer
		#10 in = -16'd32767; op = 1'b1;
        #10 $finish;
    end
endmodule*/
